/*! \file bcm56960_a0_bcmtm_sid_unique_acc.c
 *
 * Unique access memory routines for bcm56960_a0 device.
 */
/*
 * Copyright: (c) 2018 Broadcom. All Rights Reserved. "Broadcom" refers to 
 * Broadcom Limited and/or its subsidiaries.
 * 
 * Broadcom Switch Software License
 * 
 * This license governs the use of the accompanying Broadcom software. Your 
 * use of the software indicates your acceptance of the terms and conditions 
 * of this license. If you do not agree to the terms and conditions of this 
 * license, do not use the software.
 * 1. Definitions
 *    "Licensor" means any person or entity that distributes its Work.
 *    "Software" means the original work of authorship made available under 
 *    this license.
 *    "Work" means the Software and any additions to or derivative works of 
 *    the Software that are made available under this license.
 *    The terms "reproduce," "reproduction," "derivative works," and 
 *    "distribution" have the meaning as provided under U.S. copyright law.
 *    Works, including the Software, are "made available" under this license 
 *    by including in or with the Work either (a) a copyright notice 
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 * 2. Grant of Copyright License
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 * 3. Grant of Patent License
 *    Subject to the terms and conditions of this license, each Licensor 
 *    grants to you a perpetual, worldwide, non-exclusive, and royalty-free 
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 * 7. Limitations
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 *    intended for use, with a Broadcom switch integrated circuit.
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 *    reverse engineer, decompile, or attempt to ascertain the underlying 
 *    technology of a Broadcom switch integrated circuit.
 * 8. Termination
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 * 10. Limitation of Liability
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 *    THEORY, WHETHER IN TORT (INCLUDING NEGLIGENCE), CONTRACT, OR OTHERWISE 
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 */

#include <bsl/bsl.h>
#include <shr/shr_debug.h>

#include <bcmdrd/bcmdrd_types.h>
#include <bcmdrd/bcmdrd_symbols.h>

#include <bcmtm/bcmtm_types.h>
#include <bcmtm/bcmtm_internal_socmem_glue.h>

#include <bcmbd/chip/bcm56960_a0_acc.h>
#include <bcmdrd/chip/bcm56960_a0_enum.h>

#include <bcm56960_a0/bcm56960_a0_bcmtm_sid_alias.h>
#include <bcm56960_a0/bcm56960_a0_bcmtm_drv.h>

/*******************************************************************************
 * Local definitions
 */
#define MAX_UNIQUE_ACC_PT 17

typedef struct bcmtm_pt_unique_acc_list_s {
    bcmdrd_sid_t base_sid;
    bcmdrd_sid_t unique_sid_list[MAX_UNIQUE_ACC_PT];
} bcmtm_pt_unique_acc_list_t;

static bcmtm_pt_unique_acc_list_t bcm56960_a0_bcmtm_unique_reg_list[] = {
    {
        CT_PURGE_CNTr,
        {
            CT_PURGE_CNT_XPE0r,
            CT_PURGE_CNT_XPE1r,
            CT_PURGE_CNT_XPE2r,
            CT_PURGE_CNT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILEr,
        {
            MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE0r,
            MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE1r,
            MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE2r,
            MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_MCUC_BST_THRESHOLDr,
        {
            MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE0r,
            MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE1r,
            MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE2r,
            MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_MC_BST_THRESHOLDr,
        {
            MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE0r,
            MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE1r,
            MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE2r,
            MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_RED_RESUME_LIMITr,
        {
            MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE0r,
            MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE1r,
            MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE2r,
            MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_RED_SHARED_LIMITr,
        {
            MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE0r,
            MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE1r,
            MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE2r,
            MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_RESUME_LIMITr,
        {
            MMU_THDM_DB_POOL_RESUME_LIMIT_XPE0r,
            MMU_THDM_DB_POOL_RESUME_LIMIT_XPE1r,
            MMU_THDM_DB_POOL_RESUME_LIMIT_XPE2r,
            MMU_THDM_DB_POOL_RESUME_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_SHARED_LIMITr,
        {
            MMU_THDM_DB_POOL_SHARED_LIMIT_XPE0r,
            MMU_THDM_DB_POOL_SHARED_LIMIT_XPE1r,
            MMU_THDM_DB_POOL_SHARED_LIMIT_XPE2r,
            MMU_THDM_DB_POOL_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_YELLOW_RESUME_LIMITr,
        {
            MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE0r,
            MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE1r,
            MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE2r,
            MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_POOL_YELLOW_SHARED_LIMITr,
        {
            MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE0r,
            MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE1r,
            MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE2r,
            MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_PORTSP_BST_THRESHOLDr,
        {
            MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE0r,
            MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE1r,
            MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE2r,
            MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64r,
        {
            MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE0r,
            MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE1r,
            MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE2r,
            MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64r,
        {
            MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE0r,
            MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE1r,
            MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE2r,
            MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_PORTSP_SHARED_COUNTr,
        {
            MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE0r,
            MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE1r,
            MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE2r,
            MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SELr,
        {
            MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE0r,
            MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE1r,
            MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE2r,
            MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64r,
        {
            MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE0r,
            MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE1r,
            MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE2r,
            MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILEr,
        {
            MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE0r,
            MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE1r,
            MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE2r,
            MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILEr,
        {
            MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE0r,
            MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE1r,
            MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE2r,
            MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_MC_BST_THRESHOLDr,
        {
            MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE0r,
            MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE1r,
            MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE2r,
            MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_RED_RESUME_LIMITr,
        {
            MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE0r,
            MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE1r,
            MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE2r,
            MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_RED_SHARED_LIMITr,
        {
            MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE0r,
            MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE1r,
            MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE2r,
            MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_RESUME_LIMITr,
        {
            MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE0r,
            MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE1r,
            MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE2r,
            MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_SHARED_LIMITr,
        {
            MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE0r,
            MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE1r,
            MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE2r,
            MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMITr,
        {
            MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE0r,
            MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE1r,
            MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE2r,
            MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMITr,
        {
            MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE0r,
            MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE1r,
            MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE2r,
            MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_BST_THRESHOLDr,
        {
            MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE0r,
            MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE1r,
            MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE2r,
            MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64r,
        {
            MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE0r,
            MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE1r,
            MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE2r,
            MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64r,
        {
            MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE0r,
            MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE1r,
            MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE2r,
            MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_SHARED_COUNTr,
        {
            MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE0r,
            MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE1r,
            MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE2r,
            MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SELr,
        {
            MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE0r,
            MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE1r,
            MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE2r,
            MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64r,
        {
            MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE0r,
            MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE1r,
            MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE2r,
            MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILEr,
        {
            MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE0r,
            MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE1r,
            MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE2r,
            MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDR_DB_BST_THRESHOLD_PRIQr,
        {
            MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE0r,
            MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE1r,
            MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE2r,
            MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDR_DB_BST_THRESHOLD_SPr,
        {
            MMU_THDR_DB_BST_THRESHOLD_SP_XPE0r,
            MMU_THDR_DB_BST_THRESHOLD_SP_XPE1r,
            MMU_THDR_DB_BST_THRESHOLD_SP_XPE2r,
            MMU_THDR_DB_BST_THRESHOLD_SP_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDR_DB_CONFIG_SPr,
        {
            MMU_THDR_DB_CONFIG_SP_XPE0r,
            MMU_THDR_DB_CONFIG_SP_XPE1r,
            MMU_THDR_DB_CONFIG_SP_XPE2r,
            MMU_THDR_DB_CONFIG_SP_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDR_DB_RESUME_COLOR_LIMIT_SPr,
        {
            MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE0r,
            MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE1r,
            MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE2r,
            MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE3r,
            INVALIDr
        },
    },
    {
        MMU_THDR_DB_SP_SHARED_LIMITr,
        {
            MMU_THDR_DB_SP_SHARED_LIMIT_XPE0r,
            MMU_THDR_DB_SP_SHARED_LIMIT_XPE1r,
            MMU_THDR_DB_SP_SHARED_LIMIT_XPE2r,
            MMU_THDR_DB_SP_SHARED_LIMIT_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_PORT_DROP_STATEr,
        {
            OP_UC_PORT_DROP_STATE_XPE0r,
            OP_UC_PORT_DROP_STATE_XPE1r,
            OP_UC_PORT_DROP_STATE_XPE2r,
            OP_UC_PORT_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_PORT_RED_DROP_STATEr,
        {
            OP_UC_PORT_RED_DROP_STATE_XPE0r,
            OP_UC_PORT_RED_DROP_STATE_XPE1r,
            OP_UC_PORT_RED_DROP_STATE_XPE2r,
            OP_UC_PORT_RED_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_PORT_YELLOW_DROP_STATEr,
        {
            OP_UC_PORT_YELLOW_DROP_STATE_XPE0r,
            OP_UC_PORT_YELLOW_DROP_STATE_XPE1r,
            OP_UC_PORT_YELLOW_DROP_STATE_XPE2r,
            OP_UC_PORT_YELLOW_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_QGROUP_DROP_STATEr,
        {
            OP_UC_QGROUP_DROP_STATE_XPE0r,
            OP_UC_QGROUP_DROP_STATE_XPE1r,
            OP_UC_QGROUP_DROP_STATE_XPE2r,
            OP_UC_QGROUP_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_QGROUP_RED_DROP_STATEr,
        {
            OP_UC_QGROUP_RED_DROP_STATE_XPE0r,
            OP_UC_QGROUP_RED_DROP_STATE_XPE1r,
            OP_UC_QGROUP_RED_DROP_STATE_XPE2r,
            OP_UC_QGROUP_RED_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_QGROUP_YELLOW_DROP_STATEr,
        {
            OP_UC_QGROUP_YELLOW_DROP_STATE_XPE0r,
            OP_UC_QGROUP_YELLOW_DROP_STATE_XPE1r,
            OP_UC_QGROUP_YELLOW_DROP_STATE_XPE2r,
            OP_UC_QGROUP_YELLOW_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_QUEUE_DROP_STATEr,
        {
            OP_UC_QUEUE_DROP_STATE_XPE0r,
            OP_UC_QUEUE_DROP_STATE_XPE1r,
            OP_UC_QUEUE_DROP_STATE_XPE2r,
            OP_UC_QUEUE_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_QUEUE_RED_DROP_STATEr,
        {
            OP_UC_QUEUE_RED_DROP_STATE_XPE0r,
            OP_UC_QUEUE_RED_DROP_STATE_XPE1r,
            OP_UC_QUEUE_RED_DROP_STATE_XPE2r,
            OP_UC_QUEUE_RED_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        OP_UC_QUEUE_YELLOW_DROP_STATEr,
        {
            OP_UC_QUEUE_YELLOW_DROP_STATE_XPE0r,
            OP_UC_QUEUE_YELLOW_DROP_STATE_XPE1r,
            OP_UC_QUEUE_YELLOW_DROP_STATE_XPE2r,
            OP_UC_QUEUE_YELLOW_DROP_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BST_PG_HDRM_PROFILEr,
        {
            THDI_BST_PG_HDRM_PROFILE_XPE0r,
            THDI_BST_PG_HDRM_PROFILE_XPE1r,
            THDI_BST_PG_HDRM_PROFILE_XPE2r,
            THDI_BST_PG_HDRM_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BST_PG_SHARED_PROFILEr,
        {
            THDI_BST_PG_SHARED_PROFILE_XPE0r,
            THDI_BST_PG_SHARED_PROFILE_XPE1r,
            THDI_BST_PG_SHARED_PROFILE_XPE2r,
            THDI_BST_PG_SHARED_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BST_SP_GLOBAL_SHARED_PROFILEr,
        {
            THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE0r,
            THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE1r,
            THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE2r,
            THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BST_SP_SHARED_PROFILEr,
        {
            THDI_BST_SP_SHARED_PROFILE_XPE0r,
            THDI_BST_SP_SHARED_PROFILE_XPE1r,
            THDI_BST_SP_SHARED_PROFILE_XPE2r,
            THDI_BST_SP_SHARED_PROFILE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BST_TRIGGER_STATUS_32r,
        {
            THDI_BST_TRIGGER_STATUS_32_XPE0r,
            THDI_BST_TRIGGER_STATUS_32_XPE1r,
            THDI_BST_TRIGGER_STATUS_32_XPE2r,
            THDI_BST_TRIGGER_STATUS_32_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BST_TRIGGER_STATUS_TYPEr,
        {
            THDI_BST_TRIGGER_STATUS_TYPE_XPE0r,
            THDI_BST_TRIGGER_STATUS_TYPE_XPE1r,
            THDI_BST_TRIGGER_STATUS_TYPE_XPE2r,
            THDI_BST_TRIGGER_STATUS_TYPE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BUFFER_CELL_LIMIT_PUBLIC_POOLr,
        {
            THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE0r,
            THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE1r,
            THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE2r,
            THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_BUFFER_CELL_LIMIT_SPr,
        {
            THDI_BUFFER_CELL_LIMIT_SP_XPE0r,
            THDI_BUFFER_CELL_LIMIT_SP_XPE1r,
            THDI_BUFFER_CELL_LIMIT_SP_XPE2r,
            THDI_BUFFER_CELL_LIMIT_SP_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_CELL_RESET_LIMIT_OFFSET_SPr,
        {
            THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE0r,
            THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE1r,
            THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE2r,
            THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_CELL_SPAP_RED_OFFSET_SPr,
        {
            THDI_CELL_SPAP_RED_OFFSET_SP_XPE0r,
            THDI_CELL_SPAP_RED_OFFSET_SP_XPE1r,
            THDI_CELL_SPAP_RED_OFFSET_SP_XPE2r,
            THDI_CELL_SPAP_RED_OFFSET_SP_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_CELL_SPAP_YELLOW_OFFSET_SPr,
        {
            THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE0r,
            THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE1r,
            THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE2r,
            THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_FLOW_CONTROL_XOFF_STATEr,
        {
            THDI_FLOW_CONTROL_XOFF_STATE_XPE0r,
            THDI_FLOW_CONTROL_XOFF_STATE_XPE1r,
            THDI_FLOW_CONTROL_XOFF_STATE_XPE2r,
            THDI_FLOW_CONTROL_XOFF_STATE_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_GLOBAL_HDRM_COUNTr,
        {
            THDI_GLOBAL_HDRM_COUNT_XPE0r,
            THDI_GLOBAL_HDRM_COUNT_XPE1r,
            THDI_GLOBAL_HDRM_COUNT_XPE2r,
            THDI_GLOBAL_HDRM_COUNT_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_GLOBAL_HDRM_RESERVEDr,
        {
            THDI_GLOBAL_HDRM_RESERVED_XPE0r,
            THDI_GLOBAL_HDRM_RESERVED_XPE1r,
            THDI_GLOBAL_HDRM_RESERVED_XPE2r,
            THDI_GLOBAL_HDRM_RESERVED_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_HDRM_BUFFER_CELL_LIMIT_HPr,
        {
            THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE0r,
            THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE1r,
            THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE2r,
            THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_MEM_INIT_STATUSr,
        {
            THDI_MEM_INIT_STATUS_XPE0r,
            THDI_MEM_INIT_STATUS_XPE1r,
            THDI_MEM_INIT_STATUS_XPE2r,
            THDI_MEM_INIT_STATUS_XPE3r,
            INVALIDr
        },
    },
    {
        THDI_PORT_LIMIT_STATESr,
        {
            THDI_PORT_LIMIT_STATES_XPE0r,
            THDI_PORT_LIMIT_STATES_XPE1r,
            THDI_PORT_LIMIT_STATES_XPE2r,
            THDI_PORT_LIMIT_STATES_XPE3r,
            INVALIDr
        },
    },
    {
        THDU_CNG_STATE_RESETr,
        {
            THDU_CNG_STATE_RESET_XPE0r,
            THDU_CNG_STATE_RESET_XPE1r,
            THDU_CNG_STATE_RESET_XPE2r,
            THDU_CNG_STATE_RESET_XPE3r,
            INVALIDr
        },
    },
    {
        THDU_OUTPUT_PORT_RX_ENABLE_64r,
        {
            THDU_OUTPUT_PORT_RX_ENABLE_64_XPE0r,
            THDU_OUTPUT_PORT_RX_ENABLE_64_XPE1r,
            THDU_OUTPUT_PORT_RX_ENABLE_64_XPE2r,
            THDU_OUTPUT_PORT_RX_ENABLE_64_XPE3r,
            INVALIDr
        },
    },
    {
        THDU_PORT_E2ECC_COS_SPIDr,
        {
            THDU_PORT_E2ECC_COS_SPID_XPE0r,
            THDU_PORT_E2ECC_COS_SPID_XPE1r,
            THDU_PORT_E2ECC_COS_SPID_XPE2r,
            THDU_PORT_E2ECC_COS_SPID_XPE3r,
            INVALIDr
        },
    },
    {
        WRED_POOL_INST_CONG_LIMIT_0r,
        {
            WRED_POOL_INST_CONG_LIMIT_0_XPE0r,
            WRED_POOL_INST_CONG_LIMIT_0_XPE1r,
            WRED_POOL_INST_CONG_LIMIT_0_XPE2r,
            WRED_POOL_INST_CONG_LIMIT_0_XPE3r,
            INVALIDr
        },
    },
    {
        WRED_POOL_INST_CONG_LIMIT_1r,
        {
            WRED_POOL_INST_CONG_LIMIT_1_XPE0r,
            WRED_POOL_INST_CONG_LIMIT_1_XPE1r,
            WRED_POOL_INST_CONG_LIMIT_1_XPE2r,
            WRED_POOL_INST_CONG_LIMIT_1_XPE3r,
            INVALIDr
        },
    },
    {
        WRED_POOL_INST_CONG_LIMIT_2r,
        {
            WRED_POOL_INST_CONG_LIMIT_2_XPE0r,
            WRED_POOL_INST_CONG_LIMIT_2_XPE1r,
            WRED_POOL_INST_CONG_LIMIT_2_XPE2r,
            WRED_POOL_INST_CONG_LIMIT_2_XPE3r,
            INVALIDr
        },
    },
    {
        WRED_POOL_INST_CONG_LIMIT_3r,
        {
            WRED_POOL_INST_CONG_LIMIT_3_XPE0r,
            WRED_POOL_INST_CONG_LIMIT_3_XPE1r,
            WRED_POOL_INST_CONG_LIMIT_3_XPE2r,
            WRED_POOL_INST_CONG_LIMIT_3_XPE3r,
            INVALIDr
        },
    },

};

static bcmtm_pt_unique_acc_list_t bcm56960_a0_bcmtm_unique_mem_list[] = {
    {
        MMU_CCP_RESEQ_MEMm,
        {
            MMU_CCP_RESEQ_MEM_XPE0_PIPE0m,
            MMU_CCP_RESEQ_MEM_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CCP_RESEQ_MEM_XPE1_PIPE2m,
            MMU_CCP_RESEQ_MEM_XPE1_PIPE3m,
            MMU_CCP_RESEQ_MEM_XPE2_PIPE0m,
            MMU_CCP_RESEQ_MEM_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CCP_RESEQ_MEM_XPE3_PIPE2m,
            MMU_CCP_RESEQ_MEM_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_CTR_MC_DROP_MEMm,
        {
            MMU_CTR_MC_DROP_MEM_XPE0_PIPE0m,
            MMU_CTR_MC_DROP_MEM_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CTR_MC_DROP_MEM_XPE1_PIPE2m,
            MMU_CTR_MC_DROP_MEM_XPE1_PIPE3m,
            MMU_CTR_MC_DROP_MEM_XPE2_PIPE0m,
            MMU_CTR_MC_DROP_MEM_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CTR_MC_DROP_MEM_XPE3_PIPE2m,
            MMU_CTR_MC_DROP_MEM_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_CTR_UC_DROP_MEMm,
        {
            MMU_CTR_UC_DROP_MEM_XPE0_PIPE0m,
            MMU_CTR_UC_DROP_MEM_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CTR_UC_DROP_MEM_XPE1_PIPE2m,
            MMU_CTR_UC_DROP_MEM_XPE1_PIPE3m,
            MMU_CTR_UC_DROP_MEM_XPE2_PIPE0m,
            MMU_CTR_UC_DROP_MEM_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CTR_UC_DROP_MEM_XPE3_PIPE2m,
            MMU_CTR_UC_DROP_MEM_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_CTR_WRED_DROP_MEMm,
        {
            MMU_CTR_WRED_DROP_MEM_XPE0_PIPE0m,
            MMU_CTR_WRED_DROP_MEM_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CTR_WRED_DROP_MEM_XPE1_PIPE2m,
            MMU_CTR_WRED_DROP_MEM_XPE1_PIPE3m,
            MMU_CTR_WRED_DROP_MEM_XPE2_PIPE0m,
            MMU_CTR_WRED_DROP_MEM_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_CTR_WRED_DROP_MEM_XPE3_PIPE2m,
            MMU_CTR_WRED_DROP_MEM_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_ENQS_PBI_DBm,
        {
            MMU_ENQS_PBI_DB_SC0_PIPE0m,
            MMU_ENQS_PBI_DB_SC0_PIPE1m,
            MMU_ENQS_PBI_DB_SC0_PIPE2m,
            MMU_ENQS_PBI_DB_SC0_PIPE3m,
            MMU_ENQS_PBI_DB_SC1_PIPE0m,
            MMU_ENQS_PBI_DB_SC1_PIPE1m,
            MMU_ENQS_PBI_DB_SC1_PIPE2m,
            MMU_ENQS_PBI_DB_SC1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_ENQX_PIPEMEM_HIm,
        {
            MMU_ENQX_PIPEMEM_HI_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_ENQX_PIPEMEM_HI_XPE0_PIPE3m,
            MMU_ENQX_PIPEMEM_HI_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_ENQX_PIPEMEM_HI_XPE1_PIPE3m,
            INVALIDm,
            MMU_ENQX_PIPEMEM_HI_XPE2_PIPE1m,
            MMU_ENQX_PIPEMEM_HI_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            MMU_ENQX_PIPEMEM_HI_XPE3_PIPE1m,
            MMU_ENQX_PIPEMEM_HI_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        MMU_ENQX_PIPEMEM_LOm,
        {
            MMU_ENQX_PIPEMEM_LO_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_ENQX_PIPEMEM_LO_XPE0_PIPE3m,
            MMU_ENQX_PIPEMEM_LO_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_ENQX_PIPEMEM_LO_XPE1_PIPE3m,
            INVALIDm,
            MMU_ENQX_PIPEMEM_LO_XPE2_PIPE1m,
            MMU_ENQX_PIPEMEM_LO_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            MMU_ENQX_PIPEMEM_LO_XPE3_PIPE1m,
            MMU_ENQX_PIPEMEM_LO_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        MMU_EPRG_MEMm,
        {
            MMU_EPRG_MEM_XPE0m,
            MMU_EPRG_MEM_XPE1m,
            MMU_EPRG_MEM_XPE2m,
            MMU_EPRG_MEM_XPE3m,
            INVALIDm
        },
    },
    {
        MMU_PQE0_MEMm,
        {
            MMU_PQE0_MEM_XPE0m,
            MMU_PQE0_MEM_XPE1m,
            MMU_PQE0_MEM_XPE2m,
            MMU_PQE0_MEM_XPE3m,
            INVALIDm
        },
    },
    {
        MMU_PQE1_MEMm,
        {
            MMU_PQE1_MEM_XPE0m,
            MMU_PQE1_MEM_XPE1m,
            MMU_PQE1_MEM_XPE2m,
            MMU_PQE1_MEM_XPE3m,
            INVALIDm
        },
    },
    {
        MMU_REPL_GROUP_INITIAL_COPY_COUNTm,
        {
            MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC0m,
            MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC1m,
            INVALIDm
        },
    },
    {
        MMU_REPL_GROUP_INITIAL_COPY_COUNT0m,
        {
            MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC0m,
            MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC1m,
            INVALIDm
        },
    },
    {
        MMU_REPL_GROUP_INITIAL_COPY_COUNT1m,
        {
            MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC0m,
            MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC1m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_PORTSP_BSTm,
        {
            MMU_THDM_DB_PORTSP_BST_XPE0_PIPE0m,
            MMU_THDM_DB_PORTSP_BST_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_PORTSP_BST_XPE1_PIPE2m,
            MMU_THDM_DB_PORTSP_BST_XPE1_PIPE3m,
            MMU_THDM_DB_PORTSP_BST_XPE2_PIPE0m,
            MMU_THDM_DB_PORTSP_BST_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_PORTSP_BST_XPE3_PIPE2m,
            MMU_THDM_DB_PORTSP_BST_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_PORTSP_CONFIGm,
        {
            MMU_THDM_DB_PORTSP_CONFIG_PIPE0m,
            MMU_THDM_DB_PORTSP_CONFIG_PIPE1m,
            MMU_THDM_DB_PORTSP_CONFIG_PIPE2m,
            MMU_THDM_DB_PORTSP_CONFIG_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_PORTSP_CONFIG_Am,
        {
            MMU_THDM_DB_PORTSP_CONFIG_A_PIPE0m,
            MMU_THDM_DB_PORTSP_CONFIG_A_PIPE1m,
            MMU_THDM_DB_PORTSP_CONFIG_A_PIPE2m,
            MMU_THDM_DB_PORTSP_CONFIG_A_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_PORTSP_CONFIG_Bm,
        {
            MMU_THDM_DB_PORTSP_CONFIG_B_PIPE0m,
            MMU_THDM_DB_PORTSP_CONFIG_B_PIPE1m,
            MMU_THDM_DB_PORTSP_CONFIG_B_PIPE2m,
            MMU_THDM_DB_PORTSP_CONFIG_B_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_PORTSP_CONFIG_Cm,
        {
            MMU_THDM_DB_PORTSP_CONFIG_C_PIPE0m,
            MMU_THDM_DB_PORTSP_CONFIG_C_PIPE1m,
            MMU_THDM_DB_PORTSP_CONFIG_C_PIPE2m,
            MMU_THDM_DB_PORTSP_CONFIG_C_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_BSTm,
        {
            MMU_THDM_DB_QUEUE_BST_XPE0_PIPE0m,
            MMU_THDM_DB_QUEUE_BST_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_QUEUE_BST_XPE1_PIPE2m,
            MMU_THDM_DB_QUEUE_BST_XPE1_PIPE3m,
            MMU_THDM_DB_QUEUE_BST_XPE2_PIPE0m,
            MMU_THDM_DB_QUEUE_BST_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_QUEUE_BST_XPE3_PIPE2m,
            MMU_THDM_DB_QUEUE_BST_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_CONFIGm,
        {
            MMU_THDM_DB_QUEUE_CONFIG_PIPE0m,
            MMU_THDM_DB_QUEUE_CONFIG_PIPE1m,
            MMU_THDM_DB_QUEUE_CONFIG_PIPE2m,
            MMU_THDM_DB_QUEUE_CONFIG_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_CONFIG_Am,
        {
            MMU_THDM_DB_QUEUE_CONFIG_A_PIPE0m,
            MMU_THDM_DB_QUEUE_CONFIG_A_PIPE1m,
            MMU_THDM_DB_QUEUE_CONFIG_A_PIPE2m,
            MMU_THDM_DB_QUEUE_CONFIG_A_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_CONFIG_Bm,
        {
            MMU_THDM_DB_QUEUE_CONFIG_B_PIPE0m,
            MMU_THDM_DB_QUEUE_CONFIG_B_PIPE1m,
            MMU_THDM_DB_QUEUE_CONFIG_B_PIPE2m,
            MMU_THDM_DB_QUEUE_CONFIG_B_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_CONFIG_Cm,
        {
            MMU_THDM_DB_QUEUE_CONFIG_C_PIPE0m,
            MMU_THDM_DB_QUEUE_CONFIG_C_PIPE1m,
            MMU_THDM_DB_QUEUE_CONFIG_C_PIPE2m,
            MMU_THDM_DB_QUEUE_CONFIG_C_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_COUNTm,
        {
            MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE0m,
            MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE2m,
            MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE3m,
            MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE0m,
            MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE2m,
            MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_OFFSETm,
        {
            MMU_THDM_DB_QUEUE_OFFSET_PIPE0m,
            MMU_THDM_DB_QUEUE_OFFSET_PIPE1m,
            MMU_THDM_DB_QUEUE_OFFSET_PIPE2m,
            MMU_THDM_DB_QUEUE_OFFSET_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_OFFSET_Am,
        {
            MMU_THDM_DB_QUEUE_OFFSET_A_PIPE0m,
            MMU_THDM_DB_QUEUE_OFFSET_A_PIPE1m,
            MMU_THDM_DB_QUEUE_OFFSET_A_PIPE2m,
            MMU_THDM_DB_QUEUE_OFFSET_A_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_OFFSET_Bm,
        {
            MMU_THDM_DB_QUEUE_OFFSET_B_PIPE0m,
            MMU_THDM_DB_QUEUE_OFFSET_B_PIPE1m,
            MMU_THDM_DB_QUEUE_OFFSET_B_PIPE2m,
            MMU_THDM_DB_QUEUE_OFFSET_B_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_OFFSET_Cm,
        {
            MMU_THDM_DB_QUEUE_OFFSET_C_PIPE0m,
            MMU_THDM_DB_QUEUE_OFFSET_C_PIPE1m,
            MMU_THDM_DB_QUEUE_OFFSET_C_PIPE2m,
            MMU_THDM_DB_QUEUE_OFFSET_C_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_DB_QUEUE_RESUMEm,
        {
            MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE0m,
            MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE2m,
            MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE3m,
            MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE0m,
            MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE2m,
            MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_BSTm,
        {
            MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE0m,
            MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE2m,
            MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE3m,
            MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE0m,
            MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE2m,
            MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_CONFIGm,
        {
            MMU_THDM_MCQE_PORTSP_CONFIG_PIPE0m,
            MMU_THDM_MCQE_PORTSP_CONFIG_PIPE1m,
            MMU_THDM_MCQE_PORTSP_CONFIG_PIPE2m,
            MMU_THDM_MCQE_PORTSP_CONFIG_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_CONFIG_Am,
        {
            MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE0m,
            MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE1m,
            MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE2m,
            MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_CONFIG_Bm,
        {
            MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE0m,
            MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE1m,
            MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE2m,
            MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_PORTSP_CONFIG_Cm,
        {
            MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE0m,
            MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE1m,
            MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE2m,
            MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_BSTm,
        {
            MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE0m,
            MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE2m,
            MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE3m,
            MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE0m,
            MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE2m,
            MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_CONFIGm,
        {
            MMU_THDM_MCQE_QUEUE_CONFIG_PIPE0m,
            MMU_THDM_MCQE_QUEUE_CONFIG_PIPE1m,
            MMU_THDM_MCQE_QUEUE_CONFIG_PIPE2m,
            MMU_THDM_MCQE_QUEUE_CONFIG_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_CONFIG_Am,
        {
            MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE0m,
            MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE1m,
            MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE2m,
            MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_CONFIG_Bm,
        {
            MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE0m,
            MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE1m,
            MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE2m,
            MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_CONFIG_Cm,
        {
            MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE0m,
            MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE1m,
            MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE2m,
            MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_COUNTm,
        {
            MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE0m,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE2m,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE3m,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE0m,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE2m,
            MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_OFFSETm,
        {
            MMU_THDM_MCQE_QUEUE_OFFSET_PIPE0m,
            MMU_THDM_MCQE_QUEUE_OFFSET_PIPE1m,
            MMU_THDM_MCQE_QUEUE_OFFSET_PIPE2m,
            MMU_THDM_MCQE_QUEUE_OFFSET_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_OFFSET_Am,
        {
            MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE0m,
            MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE1m,
            MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE2m,
            MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_OFFSET_Bm,
        {
            MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE0m,
            MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE1m,
            MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE2m,
            MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_OFFSET_Cm,
        {
            MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE0m,
            MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE1m,
            MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE2m,
            MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDM_MCQE_QUEUE_RESUMEm,
        {
            MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE0m,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE2m,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE3m,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE0m,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE2m,
            MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_BST_PORTm,
        {
            MMU_THDU_BST_PORT_XPE0_PIPE0m,
            MMU_THDU_BST_PORT_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_BST_PORT_XPE1_PIPE2m,
            MMU_THDU_BST_PORT_XPE1_PIPE3m,
            MMU_THDU_BST_PORT_XPE2_PIPE0m,
            MMU_THDU_BST_PORT_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_BST_PORT_XPE3_PIPE2m,
            MMU_THDU_BST_PORT_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_BST_QGROUPm,
        {
            MMU_THDU_BST_QGROUP_XPE0_PIPE0m,
            MMU_THDU_BST_QGROUP_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_BST_QGROUP_XPE1_PIPE2m,
            MMU_THDU_BST_QGROUP_XPE1_PIPE3m,
            MMU_THDU_BST_QGROUP_XPE2_PIPE0m,
            MMU_THDU_BST_QGROUP_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_BST_QGROUP_XPE3_PIPE2m,
            MMU_THDU_BST_QGROUP_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_BST_QUEUEm,
        {
            MMU_THDU_BST_QUEUE_XPE0_PIPE0m,
            MMU_THDU_BST_QUEUE_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_BST_QUEUE_XPE1_PIPE2m,
            MMU_THDU_BST_QUEUE_XPE1_PIPE3m,
            MMU_THDU_BST_QUEUE_XPE2_PIPE0m,
            MMU_THDU_BST_QUEUE_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_BST_QUEUE_XPE3_PIPE2m,
            MMU_THDU_BST_QUEUE_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_PORTm,
        {
            MMU_THDU_CONFIG_PORT_PIPE0m,
            MMU_THDU_CONFIG_PORT_PIPE1m,
            MMU_THDU_CONFIG_PORT_PIPE2m,
            MMU_THDU_CONFIG_PORT_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_PORT0m,
        {
            MMU_THDU_CONFIG_PORT0_PIPE0m,
            MMU_THDU_CONFIG_PORT0_PIPE1m,
            MMU_THDU_CONFIG_PORT0_PIPE2m,
            MMU_THDU_CONFIG_PORT0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_PORT1m,
        {
            MMU_THDU_CONFIG_PORT1_PIPE0m,
            MMU_THDU_CONFIG_PORT1_PIPE1m,
            MMU_THDU_CONFIG_PORT1_PIPE2m,
            MMU_THDU_CONFIG_PORT1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_QGROUPm,
        {
            MMU_THDU_CONFIG_QGROUP_PIPE0m,
            MMU_THDU_CONFIG_QGROUP_PIPE1m,
            MMU_THDU_CONFIG_QGROUP_PIPE2m,
            MMU_THDU_CONFIG_QGROUP_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_QGROUP0m,
        {
            MMU_THDU_CONFIG_QGROUP0_PIPE0m,
            MMU_THDU_CONFIG_QGROUP0_PIPE1m,
            MMU_THDU_CONFIG_QGROUP0_PIPE2m,
            MMU_THDU_CONFIG_QGROUP0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_QGROUP1m,
        {
            MMU_THDU_CONFIG_QGROUP1_PIPE0m,
            MMU_THDU_CONFIG_QGROUP1_PIPE1m,
            MMU_THDU_CONFIG_QGROUP1_PIPE2m,
            MMU_THDU_CONFIG_QGROUP1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_QUEUEm,
        {
            MMU_THDU_CONFIG_QUEUE_PIPE0m,
            MMU_THDU_CONFIG_QUEUE_PIPE1m,
            MMU_THDU_CONFIG_QUEUE_PIPE2m,
            MMU_THDU_CONFIG_QUEUE_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_QUEUE0m,
        {
            MMU_THDU_CONFIG_QUEUE0_PIPE0m,
            MMU_THDU_CONFIG_QUEUE0_PIPE1m,
            MMU_THDU_CONFIG_QUEUE0_PIPE2m,
            MMU_THDU_CONFIG_QUEUE0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_CONFIG_QUEUE1m,
        {
            MMU_THDU_CONFIG_QUEUE1_PIPE0m,
            MMU_THDU_CONFIG_QUEUE1_PIPE1m,
            MMU_THDU_CONFIG_QUEUE1_PIPE2m,
            MMU_THDU_CONFIG_QUEUE1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_COUNTER_PORTm,
        {
            MMU_THDU_COUNTER_PORT_XPE0_PIPE0m,
            MMU_THDU_COUNTER_PORT_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_COUNTER_PORT_XPE1_PIPE2m,
            MMU_THDU_COUNTER_PORT_XPE1_PIPE3m,
            MMU_THDU_COUNTER_PORT_XPE2_PIPE0m,
            MMU_THDU_COUNTER_PORT_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_COUNTER_PORT_XPE3_PIPE2m,
            MMU_THDU_COUNTER_PORT_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_COUNTER_QGROUPm,
        {
            MMU_THDU_COUNTER_QGROUP_XPE0_PIPE0m,
            MMU_THDU_COUNTER_QGROUP_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_COUNTER_QGROUP_XPE1_PIPE2m,
            MMU_THDU_COUNTER_QGROUP_XPE1_PIPE3m,
            MMU_THDU_COUNTER_QGROUP_XPE2_PIPE0m,
            MMU_THDU_COUNTER_QGROUP_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_COUNTER_QGROUP_XPE3_PIPE2m,
            MMU_THDU_COUNTER_QGROUP_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_COUNTER_QUEUEm,
        {
            MMU_THDU_COUNTER_QUEUE_XPE0_PIPE0m,
            MMU_THDU_COUNTER_QUEUE_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_COUNTER_QUEUE_XPE1_PIPE2m,
            MMU_THDU_COUNTER_QUEUE_XPE1_PIPE3m,
            MMU_THDU_COUNTER_QUEUE_XPE2_PIPE0m,
            MMU_THDU_COUNTER_QUEUE_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_COUNTER_QUEUE_XPE3_PIPE2m,
            MMU_THDU_COUNTER_QUEUE_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_OFFSET_QGROUPm,
        {
            MMU_THDU_OFFSET_QGROUP_PIPE0m,
            MMU_THDU_OFFSET_QGROUP_PIPE1m,
            MMU_THDU_OFFSET_QGROUP_PIPE2m,
            MMU_THDU_OFFSET_QGROUP_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_OFFSET_QGROUP0m,
        {
            MMU_THDU_OFFSET_QGROUP0_PIPE0m,
            MMU_THDU_OFFSET_QGROUP0_PIPE1m,
            MMU_THDU_OFFSET_QGROUP0_PIPE2m,
            MMU_THDU_OFFSET_QGROUP0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_OFFSET_QGROUP1m,
        {
            MMU_THDU_OFFSET_QGROUP1_PIPE0m,
            MMU_THDU_OFFSET_QGROUP1_PIPE1m,
            MMU_THDU_OFFSET_QGROUP1_PIPE2m,
            MMU_THDU_OFFSET_QGROUP1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_OFFSET_QUEUEm,
        {
            MMU_THDU_OFFSET_QUEUE_PIPE0m,
            MMU_THDU_OFFSET_QUEUE_PIPE1m,
            MMU_THDU_OFFSET_QUEUE_PIPE2m,
            MMU_THDU_OFFSET_QUEUE_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_OFFSET_QUEUE0m,
        {
            MMU_THDU_OFFSET_QUEUE0_PIPE0m,
            MMU_THDU_OFFSET_QUEUE0_PIPE1m,
            MMU_THDU_OFFSET_QUEUE0_PIPE2m,
            MMU_THDU_OFFSET_QUEUE0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_OFFSET_QUEUE1m,
        {
            MMU_THDU_OFFSET_QUEUE1_PIPE0m,
            MMU_THDU_OFFSET_QUEUE1_PIPE1m,
            MMU_THDU_OFFSET_QUEUE1_PIPE2m,
            MMU_THDU_OFFSET_QUEUE1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_Q_TO_QGRP_MAPm,
        {
            MMU_THDU_Q_TO_QGRP_MAP_PIPE0m,
            MMU_THDU_Q_TO_QGRP_MAP_PIPE1m,
            MMU_THDU_Q_TO_QGRP_MAP_PIPE2m,
            MMU_THDU_Q_TO_QGRP_MAP_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_Q_TO_QGRP_MAP0m,
        {
            MMU_THDU_Q_TO_QGRP_MAP0_PIPE0m,
            MMU_THDU_Q_TO_QGRP_MAP0_PIPE1m,
            MMU_THDU_Q_TO_QGRP_MAP0_PIPE2m,
            MMU_THDU_Q_TO_QGRP_MAP0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_Q_TO_QGRP_MAP1m,
        {
            MMU_THDU_Q_TO_QGRP_MAP1_PIPE0m,
            MMU_THDU_Q_TO_QGRP_MAP1_PIPE1m,
            MMU_THDU_Q_TO_QGRP_MAP1_PIPE2m,
            MMU_THDU_Q_TO_QGRP_MAP1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_Q_TO_QGRP_MAP2m,
        {
            MMU_THDU_Q_TO_QGRP_MAP2_PIPE0m,
            MMU_THDU_Q_TO_QGRP_MAP2_PIPE1m,
            MMU_THDU_Q_TO_QGRP_MAP2_PIPE2m,
            MMU_THDU_Q_TO_QGRP_MAP2_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_RESUME_PORTm,
        {
            MMU_THDU_RESUME_PORT_PIPE0m,
            MMU_THDU_RESUME_PORT_PIPE1m,
            MMU_THDU_RESUME_PORT_PIPE2m,
            MMU_THDU_RESUME_PORT_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_RESUME_PORT0m,
        {
            MMU_THDU_RESUME_PORT0_PIPE0m,
            MMU_THDU_RESUME_PORT0_PIPE1m,
            MMU_THDU_RESUME_PORT0_PIPE2m,
            MMU_THDU_RESUME_PORT0_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_RESUME_PORT1m,
        {
            MMU_THDU_RESUME_PORT1_PIPE0m,
            MMU_THDU_RESUME_PORT1_PIPE1m,
            MMU_THDU_RESUME_PORT1_PIPE2m,
            MMU_THDU_RESUME_PORT1_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_RESUME_PORT2m,
        {
            MMU_THDU_RESUME_PORT2_PIPE0m,
            MMU_THDU_RESUME_PORT2_PIPE1m,
            MMU_THDU_RESUME_PORT2_PIPE2m,
            MMU_THDU_RESUME_PORT2_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_RESUME_QGROUPm,
        {
            MMU_THDU_RESUME_QGROUP_XPE0_PIPE0m,
            MMU_THDU_RESUME_QGROUP_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_RESUME_QGROUP_XPE1_PIPE2m,
            MMU_THDU_RESUME_QGROUP_XPE1_PIPE3m,
            MMU_THDU_RESUME_QGROUP_XPE2_PIPE0m,
            MMU_THDU_RESUME_QGROUP_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_RESUME_QGROUP_XPE3_PIPE2m,
            MMU_THDU_RESUME_QGROUP_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_THDU_RESUME_QUEUEm,
        {
            MMU_THDU_RESUME_QUEUE_XPE0_PIPE0m,
            MMU_THDU_RESUME_QUEUE_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_RESUME_QUEUE_XPE1_PIPE2m,
            MMU_THDU_RESUME_QUEUE_XPE1_PIPE3m,
            MMU_THDU_RESUME_QUEUE_XPE2_PIPE0m,
            MMU_THDU_RESUME_QUEUE_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_THDU_RESUME_QUEUE_XPE3_PIPE2m,
            MMU_THDU_RESUME_QUEUE_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_AVG_QSIZEm,
        {
            MMU_WRED_AVG_QSIZE_XPE0_PIPE0m,
            MMU_WRED_AVG_QSIZE_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_AVG_QSIZE_XPE1_PIPE2m,
            MMU_WRED_AVG_QSIZE_XPE1_PIPE3m,
            MMU_WRED_AVG_QSIZE_XPE2_PIPE0m,
            MMU_WRED_AVG_QSIZE_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_AVG_QSIZE_XPE3_PIPE2m,
            MMU_WRED_AVG_QSIZE_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_CONFIGm,
        {
            MMU_WRED_CONFIG_XPE0_PIPE0m,
            MMU_WRED_CONFIG_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_CONFIG_XPE1_PIPE2m,
            MMU_WRED_CONFIG_XPE1_PIPE3m,
            MMU_WRED_CONFIG_XPE2_PIPE0m,
            MMU_WRED_CONFIG_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_CONFIG_XPE3_PIPE2m,
            MMU_WRED_CONFIG_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_PORT_SP_DROP_THDm,
        {
            MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE0m,
            MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE2m,
            MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE3m,
            MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE0m,
            MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE2m,
            MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_PORT_SP_DROP_THD_MARKm,
        {
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE0m,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE2m,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE3m,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE0m,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE2m,
            MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_PORT_SP_SHARED_COUNTm,
        {
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE0m,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2m,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE0m,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2m,
            MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_UC_QUEUE_DROP_THD_0m,
        {
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE0m,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE2m,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE3m,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE0m,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE2m,
            MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_UC_QUEUE_DROP_THD_1m,
        {
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE0m,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE2m,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE3m,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE0m,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE2m,
            MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_UC_QUEUE_DROP_THD_MARKm,
        {
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE0m,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE2m,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE3m,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE0m,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE2m,
            MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_UC_QUEUE_TOTAL_COUNTm,
        {
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE0m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE2m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE3m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE0m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE2m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTEm,
        {
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE0m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE2m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE3m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE0m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE1m,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            INVALIDm,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE2m,
            MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE3m,
            INVALIDm
        },
    },
    {
        THDI_PORT_PG_BSTm,
        {
            THDI_PORT_PG_BST_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_BST_XPE0_PIPE3m,
            THDI_PORT_PG_BST_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_BST_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_PG_BST_XPE2_PIPE1m,
            THDI_PORT_PG_BST_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_BST_XPE3_PIPE1m,
            THDI_PORT_PG_BST_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_PG_CNTRS_RT1m,
        {
            THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE3m,
            THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE1m,
            THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE1m,
            THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_PG_CNTRS_RT2m,
        {
            THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE3m,
            THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE1m,
            THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE1m,
            THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_PG_CNTRS_SH1m,
        {
            THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE3m,
            THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE1m,
            THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE1m,
            THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_PG_CNTRS_SH2m,
        {
            THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE3m,
            THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE1m,
            THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE1m,
            THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_PG_CONFIGm,
        {
            THDI_PORT_PG_CONFIG_PIPE0m,
            THDI_PORT_PG_CONFIG_PIPE1m,
            THDI_PORT_PG_CONFIG_PIPE2m,
            THDI_PORT_PG_CONFIG_PIPE3m,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_BSTm,
        {
            THDI_PORT_SP_BST_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_BST_XPE0_PIPE3m,
            THDI_PORT_SP_BST_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_BST_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_SP_BST_XPE2_PIPE1m,
            THDI_PORT_SP_BST_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_BST_XPE3_PIPE1m,
            THDI_PORT_SP_BST_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_CNTRS_RTm,
        {
            THDI_PORT_SP_CNTRS_RT_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_CNTRS_RT_XPE0_PIPE3m,
            THDI_PORT_SP_CNTRS_RT_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_CNTRS_RT_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_SP_CNTRS_RT_XPE2_PIPE1m,
            THDI_PORT_SP_CNTRS_RT_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_CNTRS_RT_XPE3_PIPE1m,
            THDI_PORT_SP_CNTRS_RT_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_CNTRS_SHm,
        {
            THDI_PORT_SP_CNTRS_SH_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_CNTRS_SH_XPE0_PIPE3m,
            THDI_PORT_SP_CNTRS_SH_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_CNTRS_SH_XPE1_PIPE3m,
            INVALIDm,
            THDI_PORT_SP_CNTRS_SH_XPE2_PIPE1m,
            THDI_PORT_SP_CNTRS_SH_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            THDI_PORT_SP_CNTRS_SH_XPE3_PIPE1m,
            THDI_PORT_SP_CNTRS_SH_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_CONFIGm,
        {
            THDI_PORT_SP_CONFIG_PIPE0m,
            THDI_PORT_SP_CONFIG_PIPE1m,
            THDI_PORT_SP_CONFIG_PIPE2m,
            THDI_PORT_SP_CONFIG_PIPE3m,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_CONFIG0m,
        {
            THDI_PORT_SP_CONFIG0_PIPE0m,
            THDI_PORT_SP_CONFIG0_PIPE1m,
            THDI_PORT_SP_CONFIG0_PIPE2m,
            THDI_PORT_SP_CONFIG0_PIPE3m,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_CONFIG1m,
        {
            THDI_PORT_SP_CONFIG1_PIPE0m,
            THDI_PORT_SP_CONFIG1_PIPE1m,
            THDI_PORT_SP_CONFIG1_PIPE2m,
            THDI_PORT_SP_CONFIG1_PIPE3m,
            INVALIDm
        },
    },
    {
        THDI_PORT_SP_CONFIG2m,
        {
            THDI_PORT_SP_CONFIG2_PIPE0m,
            THDI_PORT_SP_CONFIG2_PIPE1m,
            THDI_PORT_SP_CONFIG2_PIPE2m,
            THDI_PORT_SP_CONFIG2_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_MTRO_EGRMETERINGBUCKET_MEMm,
        {
            MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE0m,
            MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE1m,
            MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE2m,
            MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_MTRO_BUCKET_L0_MEMm,
        {
            MMU_MTRO_BUCKET_L0_MEM_PIPE0m,
            MMU_MTRO_BUCKET_L0_MEM_PIPE1m,
            MMU_MTRO_BUCKET_L0_MEM_PIPE2m,
            MMU_MTRO_BUCKET_L0_MEM_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_MTRO_BUCKET_L1_MEMm,
        {
            MMU_MTRO_BUCKET_L1_MEM_PIPE0m,
            MMU_MTRO_BUCKET_L1_MEM_PIPE1m,
            MMU_MTRO_BUCKET_L1_MEM_PIPE2m,
            MMU_MTRO_BUCKET_L1_MEM_PIPE3m,
            INVALIDm
        },
    },
    {
        Q_SCHED_L0_ACCUM_COMP_MEMm,
        {
            Q_SCHED_L0_ACCUM_COMP_MEM_PIPE0m,
            Q_SCHED_L0_ACCUM_COMP_MEM_PIPE1m,
            Q_SCHED_L0_ACCUM_COMP_MEM_PIPE2m,
            Q_SCHED_L0_ACCUM_COMP_MEM_PIPE3m,
            INVALIDm
        },
    },

    {
        Q_SCHED_L0_CREDIT_MEMm,
        {
            Q_SCHED_L0_CREDIT_MEM_PIPE0m,
            Q_SCHED_L0_CREDIT_MEM_PIPE1m,
            Q_SCHED_L0_CREDIT_MEM_PIPE2m,
            Q_SCHED_L0_CREDIT_MEM_PIPE3m,
            INVALIDm
        },
    },

    {
        Q_SCHED_L0_WEIGHT_MEMm,
        {
            Q_SCHED_L0_WEIGHT_MEM_PIPE0m,
            Q_SCHED_L0_WEIGHT_MEM_PIPE1m,
            Q_SCHED_L0_WEIGHT_MEM_PIPE2m,
            Q_SCHED_L0_WEIGHT_MEM_PIPE3m,
            INVALIDm
        },
    },

    {
        Q_SCHED_L1_ACCUM_COMP_MEMm,
        {
            Q_SCHED_L1_ACCUM_COMP_MEM_PIPE0m,
            Q_SCHED_L1_ACCUM_COMP_MEM_PIPE1m,
            Q_SCHED_L1_ACCUM_COMP_MEM_PIPE2m,
            Q_SCHED_L1_ACCUM_COMP_MEM_PIPE3m,
            INVALIDm
        },
    },

    {
        Q_SCHED_L1_CREDIT_MEMm,
        {
            Q_SCHED_L1_CREDIT_MEM_PIPE0m,
            Q_SCHED_L1_CREDIT_MEM_PIPE1m,
            Q_SCHED_L1_CREDIT_MEM_PIPE2m,
            Q_SCHED_L1_CREDIT_MEM_PIPE3m,
            INVALIDm
        },
    },

    {
        Q_SCHED_L2_ACCUM_COMP_MEMm,
        {
            Q_SCHED_L2_ACCUM_COMP_MEM_PIPE0m,
            Q_SCHED_L2_ACCUM_COMP_MEM_PIPE1m,
            Q_SCHED_L2_ACCUM_COMP_MEM_PIPE2m,
            Q_SCHED_L2_ACCUM_COMP_MEM_PIPE3m,
            INVALIDm
        },
    },
    {
        Q_SCHED_L2_CREDIT_MEMm,
        {
            Q_SCHED_L2_CREDIT_MEM_PIPE0m,
            Q_SCHED_L2_CREDIT_MEM_PIPE1m,
            Q_SCHED_L2_CREDIT_MEM_PIPE2m,
            Q_SCHED_L2_CREDIT_MEM_PIPE3m,
            INVALIDm
        },
    },
    {
        MMU_CTR_ING_DROP_MEMm,
        {
            MMU_CTR_ING_DROP_MEM_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_CTR_ING_DROP_MEM_XPE0_PIPE3m,
            MMU_CTR_ING_DROP_MEM_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_CTR_ING_DROP_MEM_XPE1_PIPE3m,
            INVALIDm,
            MMU_CTR_ING_DROP_MEM_XPE2_PIPE1m,
            MMU_CTR_ING_DROP_MEM_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            MMU_CTR_ING_DROP_MEM_XPE3_PIPE1m,
            MMU_CTR_ING_DROP_MEM_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
    {
        MMU_CTR_COLOR_DROP_MEMm,
        {
            MMU_CTR_COLOR_DROP_MEM_XPE0_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_CTR_COLOR_DROP_MEM_XPE0_PIPE3m,
            MMU_CTR_COLOR_DROP_MEM_XPE1_PIPE0m,
            INVALIDm,
            INVALIDm,
            MMU_CTR_COLOR_DROP_MEM_XPE1_PIPE3m,
            INVALIDm,
            MMU_CTR_COLOR_DROP_MEM_XPE2_PIPE1m,
            MMU_CTR_COLOR_DROP_MEM_XPE2_PIPE2m,
            INVALIDm,
            INVALIDm,
            MMU_CTR_COLOR_DROP_MEM_XPE3_PIPE1m,
            MMU_CTR_COLOR_DROP_MEM_XPE3_PIPE2m,
            INVALIDm,
            INVALIDm
        },
    },
};

/*******************************************************************************
 * Public functions
 */
bcmdrd_sid_t
bcm56960_a0_bcmtm_pt_sid_unique_xpe_pipe(int unit, bcmdrd_sid_t sid_in,
                                         int xpe, int pipe_num)
{
    int index, arr_idx, arr_cnt;
    bcmtm_pt_unique_acc_list_t *unique_acc_db, *unique_acc = NULL;

    if (bcmdrd_pt_is_mem(unit, sid_in)) {
        unique_acc_db = bcm56960_a0_bcmtm_unique_mem_list;
        arr_cnt = COUNTOF(bcm56960_a0_bcmtm_unique_mem_list);
    } else {
        unique_acc_db = bcm56960_a0_bcmtm_unique_reg_list;
        arr_cnt = COUNTOF(bcm56960_a0_bcmtm_unique_reg_list);
    }

    for (arr_idx = 0; arr_idx < arr_cnt; arr_idx++) {
        unique_acc = &(unique_acc_db[arr_idx]);
        if (unique_acc->base_sid == sid_in) {
            break;
        }
    }

    index = ((xpe * 4 ) + pipe_num);

    /* In case of per-pipe views, xpe will be '-1'  */
    if (xpe == -1) {
        index = pipe_num;
    }

    /* In case of per-xpe views, pipe_num will be '-1'  */
    if (pipe_num == -1) {
        index = xpe;
    }

    if (index == -1) {
        return INVALIDm;
    }

    return unique_acc->unique_sid_list[index];
}

int
bcm56960_a0_bcmtm_sid_unique_acc_list_get(int unit,
                              bcmdrd_sid_t sid_in,
                              bcmpc_lport_t lport,
                              int index_in,
                              int max,
                              bcmdrd_sid_t *sid_out,
                              int *inst_out,
                              int *index_out,
                              int *count)
{
    int ix, arr_idx, arr_cnt;
    bcmdrd_sid_t invalid_sid;
    bcmtm_pt_unique_acc_list_t *unique_acc_db, *unique_acc = NULL;

    SHR_FUNC_ENTER(unit);


    if (bcmdrd_pt_is_mem(unit, sid_in)) {
        invalid_sid = INVALIDm;
        unique_acc_db = bcm56960_a0_bcmtm_unique_mem_list;
        arr_cnt = COUNTOF(bcm56960_a0_bcmtm_unique_mem_list);
    } else {
        invalid_sid = INVALIDr;
        unique_acc_db = bcm56960_a0_bcmtm_unique_reg_list;
        arr_cnt = COUNTOF(bcm56960_a0_bcmtm_unique_reg_list);
    }

    for (arr_idx = 0; arr_idx < arr_cnt; arr_idx++) {
        unique_acc = &(unique_acc_db[arr_idx]);
        if (unique_acc->base_sid == sid_in) {
            break;
        }
    }

    *count = 0;
    if (unique_acc != NULL) {
        for (ix = 0; ix < MAX_UNIQUE_ACC_PT; ix++) {
            if (unique_acc->unique_sid_list[ix] != invalid_sid) {
                if (sid_out != NULL) {
                    sid_out[*count] = unique_acc->unique_sid_list[ix];
                }
                if (index_out != NULL) {
                    index_out[*count] = index_in;
                }
                *count += 1;
            }
        }
    }


    SHR_IF_ERR_EXIT(SHR_E_NONE);

exit:
    SHR_FUNC_EXIT();
}

